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M68AR512D
8 Mbit (512K x16) 1.8V Asynchronous SRAM
FEATURES SUMMARY s SUPPLY VOLTAGE: 1.65 to 1.95V
s s s s s s s s
Figure 1. Packages
512K x 16 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 70ns SINGLE BYTE READ/WRITE LOW STANDBY CURRENT LOW VCC DATA RETENTION: 1.0V TRI-STATE COMMON I/O AUTOMATIC POWER DOWN DUAL CHIP ENABLE for EASY DEPTH EXPANSION
BGA
BGA
TFBGA48 (ZB) 6 x 7mm
TFBGA48 (ZB) 8 x 10mm
October 2002
1/19
M68AR512D
TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MAXIMUM RATING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 6. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . 9 Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . . 9 Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 10. Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 11. Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 12. UB/LB Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 13. E1 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 14. E2 Controlled, Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9. Low VCC Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TFBGA48 6x7mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline . . . . . . . . . . . . . 15 TFBGA48 6x7mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . . . . . . . . . . 15 TFBGA48 8x10mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline . . . . . . . . . . . . 16 TFBGA48 8x10mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . . . . . . . . . 16 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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M68AR512D
SUMMARY DESCRIPTION The M68AR512D is an 8 Mbit (8,388,608 bit) CMOS SRAM, organized as 524,288 words by 16 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 1.8V (150mV) supply. This device has a Chip Select pin (E2) for easy memory expansion; when it is active (E2 high) the device has an auto-
matic power-down feature, reducing the power consumption by over 99%. The M68AR512D is available in TFBGA48 (6x7mm and 8x10mm, 6x8 active ball array, 0.75 mm ball pitch) package. See the Ordering Information Scheme (Table 12) for details.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A18 Address Inputs Data Input/Output Chip Enable Output Enable Write Enable Upper Byte Enable Input Lower Byte Enable Input Supply Voltage Ground Not Connected Don't Use as Internally Connected
VCC
DQ0-DQ15 E1, E2
19 A0-A18 W E1 E2 G UB LB M68AR512D
16 DQ0-DQ15
G W UB LB VCC VSS NC DU
VSS
AI03953C
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M68AR512D
Figure 3. TFBGA Connections (Top view through package)
1
2
3
4
5
6
A
LB
G
A0
A1
A2
E2
B
DQ8
UB
A3
A4
E1
DQ0
C
DQ9
DQ10
A5
A6
DQ1
DQ2
D
VSS
DQ11
A17
A7
DQ3
VCC
E
VCC
DQ12
VSS
A16
DQ4
VSS
F
DQ14
DQ13
A14
A15
DQ5
DQ6
G
DQ15
NC
A12
A13
W
DQ7
H
A18
A8
A9
A10
A11
DU
AI03960
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M68AR512D
Figure 4. Block Diagram
A18 ROW DECODER A8 MEMORY ARRAY
DQ15 UB
(8)
I/O CIRCUITS COLUMN DECODER
DQ0 E1 E2 UB LB Ex LB
(8)
A0 (8)
A7
W
UB
(8) LB G
AI05452
MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 2. Absolute Maximum Ratings
Symbol IO (1) TA TSTG VCC VIO (2) PD Output Current Ambient Operating Temperature Storage Temperature Supply Voltage Input or Output Voltage Power Dissipation Parameter
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Value 20 -55 to 125 -65 to 150 -0.5 to 2.5 -0.5 to VCC +0.5 1
Unit mA C C V V W
Note: 1. One output at a time, not to exceed 1 second duration. 2. Up to a maximum operating VCC of 1.95V only.
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M68AR512D
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter VCC Supply Voltage Range 1 Ambient Operating Temperature Range 6 Load Capacitance (CL) Output Circuit Protection Resistance (R1) Load Resistance (R2) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Output Transition Timing Ref. Voltages -40 to 85C 30pF 15.3k 11.3k 1ns/V 0 to VCC VCC/2 VRL = 0.3VCC; VRH = 0.7VCC M68AR512D 1.65 to 1.95V 0 to 70C
Figure 5. AC Measurement I/O Waveform
Figure 6. AC Measurement Load Circuit
VCC
I/O Timing Reference Voltage R1 VCC VCC/2 0V DEVICE UNDER TEST CL R2 0.7VCC 0.3VCC
AI04831
OUT
Output Timing Reference Voltage VCC
0V
CL includes probe and 1TTL capacitance
AI03853
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M68AR512D
Table 4. Capacitance
Symbol CIN COUT Parameter(1,2) Input Capacitance on all pins (except DQ) Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 8 Unit pF pF
Note: 1. Sampled only, not 100% tested. 2. At TA = 25C, f = 1 MHz, VCC = 1.8V.
Table 5. DC Characteristics
Symbol ICC1 (1,2) ICC2 (3) ILI ILO (4) Parameter Operating Supply Current Operating Supply Current Input Leakage Current Output Leakage Current Test Condition VCC = 1.95V, f = 1/t AVAV, IOUT = 0mA VCC = 1.95V, f = 1MHz, IOUT = 0mA 0V VIN VCC 0V VOUT VCC VCC = 1.95V, E1 VCC -0.2V or E2 0.2V or UB=LB VCC -0.2V, f = 0 1.4 -0.5 IOH = -100A IOL = 100A 1.5 0.2 -1 -1 Min Typ Max 12 2 1 1 Unit mA mA A A
ISB
(3)
Standby Supply Current CMOS
1
15
A
VIH VIL VOH VOL
Note: 1. 2. 3. 4.
Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage
VCC + 0.4 0.4
V V V V
Average AC current, cycling at tAVAV minimum. E1 = VIL, E2 = VIH, UB or/and LB = VIL, VIN = VIH or VIL. E1 0.2V or E2 VCC -0.2V, LB or/and UB 0.2V, VIN 0.2V or VIN VCC -0.2V. Output disabled.
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M68AR512D
OPERATION The M68AR512D has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (E1 = High) or Chip Select is asserted (E2 = Low), or UB/LB are de-asserted (UB/LB = High). An Output Enable (G) signal provides a high speed tri-state conTable 6. Operating Modes
Operation Deselected/Power-down Deselected/Power-down Deselected/Power-down Lower Byte Read Lower Byte Write Output Disabled Upper Byte Read Upper Byte Write Word Read Word Write
Note: X = VIH or VIL.
trol, allowing fast read/write cycles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W, E1, LB and UB as summarized in the Operating Modes table (see Table 6).
E1 VIH X X VIL VIL VIL VIL VIL VIL VIL
E2 X VIL X VIH VIH VIH VIH VIH VIH VIH
W X X X VIH VIL X VIH VIL VIH VIL
G X X X VIL X VIH VIL X VIL X
LB X X VIH VIL VIL X VIH VIH VIL VIL
UB X X VIH VIH VIH X VIL VIL VIL VIL
DQ0-DQ7 Hi-Z Hi-Z Hi-Z Data Output Data Input Hi-Z Hi-Z Hi-Z Data Output Data Input
DQ8-DQ15 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Data Output Data Input Data Output Data Input
Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Read Mode The M68AR512D, when Chip Select (E2) is High, is in the read mode whenever Write Enable (W) is High with Output Enable (G) Low, and Chip Enable (E1) is asserted. This provides access to data from eight or sixteen, depending on the status of the signal UB and LB, of the 8,388,608 locations in the static memory array, specified by the 19 address inputs. Valid data will be available at the
eight or sixteen output pins within tAVQV after the last stable address, providing G is Low and E1 is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tELQV, tGLQV or tBLQV) rather than the address. Data out may be indeterminate at tELQX, tGLQX and tBLQX, but data lines will always be valid at tAVQV.
Figure 7. Address Controlled, Read Mode AC Waveforms
tAVAV A0-A18 tAVQV VALID tAXQX
DQ0-DQ7 and/or DQ8-DQ15
DATA VALID
AI03961
Note: E1 = Low, E2 = High, G = Low, W = High, UB = Low and/or LB = Low.
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M68AR512D
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
tAVAV A0-A18 tAVQV tELQV E1 VALID tAXQX tEHQZ
E2
tELQX tGLQV G tGLQX DQ0-DQ15 tBLQV UB, LB tBLQX
AI05994
tGHQZ
VALID tBHQZ
Note: Write Enable (W) = High
Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms
E1, UB, LB
E2 ICC ISB tPU 50%
AI05990
tPD
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M68AR512D
Table 7. Read and Standby Mode AC Characteristics
M68AR512D Symbol tAVAV tAVQV tAXQX (1) tBHQZ (2, 3) tBLQV tBLQX (1) tEHQZ (2, 3) tELQV tELQX (1) tGHQZ (2, 3) tGLQV tGLQX (1) tPD (4) tPU (4) Read Cycle Time Address Valid to Output Valid Data hold from address change Upper/Lower Byte Enable High to Output Hi-Z Upper/Lower Byte Enable Low to Output Valid Upper/Lower Byte Enable Low to Output Transition Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Chip Enable High to Power Down Chip Enable Low to Power Up Parameter 70 Min Max Min Max Max Min Max Max Min Max Max Min Max Min 70 70 5 25 70 5 25 70 5 25 35 5 0 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Test conditions assume transition timing reference level = 0.3VCCQ to 0.7VCCQ. 2. At any given temperature and voltage condition, tGHQZ is less than tGLQX, tBHQZ is less than tBLQX and tEHQZ is less than tELQX for any given device. 3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4. Tested initially and after any design or process changes that may affect these parameters.
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M68AR512D
Write Mode The M68AR512D, when Chip Select (E2) is High, is in the Write Mode whenever the W and E1 are Low. Either the Chip Enable Input (E1) or the Write Enable input (W) must be de-asserted during Address transitions for subsequent write cycles. When E1 or W is Low, and UB or LB is Low, write cycle begins on the W or E1 falling edge. When E1 and W are Low, and UB = LB = High, write cycle begins on the first falling edge of UB or LB. Therefore, address setup time is referenced to Write Enable, Chip Enables and UB/LB as tAVWL, tAVEL and tAVBL respectively, and is determined by the latter occurring falling edge.
The Write cycle can be terminated by the earlier rising edge of E1, W, UB and LB. If the Output is enabled (E1 = Low, E2 = High, G = Low, LB or UB = Low), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for tDVEH before the rising edge of E1 or for tDVBH before the rising edge of UB/LB, whichever occurs first, and remain valid for tWHDX, tEHDX and tBHDX respectively.
Figure 10. Write Enable Controlled, Write AC Waveforms
tAVAV A0-A18 VALID tAVWH tAVEL E1 tELWH tWHAX
E2 tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ15 DATA INPUT tDVWH tBLBH UB, LB
AI05995
tWHQX
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M68AR512D
Figure 11. Chip Enable Controlled, Write AC Waveforms
tAVAV A0-A18 VALID tAVEH tAVEL E1 tELEH tEHAX
E2 tAVWL W tEHDX DQ0-DQ15 DATA INPUT tDVEH tBLBH UB, LB
AI05996
tWLEH
Figure 12. UB/LB Controlled, Write AC Waveforms
tAVAV A0-A18 VALID tAVBH E1 tBHAX
E2 tAVWL W tWLQZ DQ0-DQ15 DATA (1) tBHDX DATA INPUT tDVBH tAVBL UB, LB
AI05997
tWLBH
tBLBH
Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applied.
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M68AR512D
Table 8. Write Mode AC Characteristics
M68AR512D Symbol tAVAV tAVBH tAVBL tAVEH tAVEL tAVWH tAVWL tBHAX tBHDX tBLBH tBLEH tBLWH tDVBH tDVEH tDVWH tEHAX tEHDX tELBH tELEH tELWH tWHAX tWHDX tWHQX (1) tWLBH tWLEH tWLQZ (1, 2) tWLWH Write Cycle Time Address Valid to LB, UB High Address Valid to LB, UB Low Address Valid to Chip Enable High Address valid to Chip Enable Low Address Valid to Write Enable High Address Valid to Write Enable Low LB, UB High to Address Transition LB, UB High to Input Transition LB, UB Low to LB, UB High LB, UB Low to Chip Enable High LB, UB Low to Write Enable High Input Valid to LB, UB High Input Valid to Chip Enable High Input Valid to Write Enable High Chip Enable High to Address Transition Chip enable High to Input Transition Chip Enable Low to LB, UB High Chip Enable Low to Chip Enable High Chip Enable Low to Write Enable High Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Output Transition Write Enable Low to LB, UB High Write Enable Low to Chip Enable High Write Enable Low to Output Hi-Z Write Enable Low to Write Enable High Parameter 70 Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Max Min 70 60 0 60 0 60 0 0 0 60 60 60 30 30 30 0 0 60 60 60 0 0 5 60 60 20 60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. At any given temperature and voltage condition, tWHQZ is less than tWLQX for any given device. 2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
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M68AR512D
Figure 13. E1 Controlled, Low VCC Data Retention AC Waveforms
DATA RETENTION MODE 1.95V VCC 1.8V
VDR > 1.0V tCDR E1 VDR - 0.2V E1 tR
AI05455
Figure 14. E2 Controlled, Low VCC Data Retention AC Waveforms
DATA RETENTION MODE 1.95V VCC 1.65V VDR > 1.0V tCDR E2 E2 0.2V
AI05475
tR
Table 9. Low VCC Data Retention Characteristics
Symbol ICCDR (1) tCDR (2) tR (2) VDR (1) Parameter Supply Current (Data Retention) Chip deselected to Data Retention Time Operation Recovery Time E1 VCC -0.2V or E2 0.2V or UB/LB VCC -0.2V, f=0 Test Condition VCC = 1.0V, E1 VCC -0.2V or E2 0.2V or UB/LB VCC -0.2V, f = 0 (3) 0 tAVAV Min Typ 0.1 Max 8 Unit A
ns ns
Supply Voltage (Data Retention)
1.0
V
Note: 1. All other Inputs at VIH VCC -0.2V or VIL 0.2V. 2. Tested initially and after any design or process changes that may affect these parameters. tAVAV is Read cycle time. 3. No input may exceed VCC +0.3V.
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M68AR512D
PACKAGE MECHANICAL Figure 15. TFBGA48 6x7mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline
D FD FE SD D1
SE E E1 BALL "A1" ddd
e e A A1 b A2
BGA-Z43
Note: Drawing is not to scale.
Table 10. TFBGA48 6x7mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SD SE 7.000 5.250 0.750 1.125 0.875 0.375 0.375 - - - - - - 6.900 0.790 0.400 6.000 3.750 0.100 7.100 0.2756 0.2067 0.0295 0.0443 0.0344 0.0148 0.0148 - - - - - - 0.2717 0.350 5.900 0.450 6.100 0.250 Min Max 1.200 0.400 0.0311 0.0157 0.2362 0.1476 0.0039 0.2795 0.0138 0.2323 0.0177 0.2402 0.0098 Typ Min Max 0.0472 0.0157 inches
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M68AR512D
Figure 16. TFBGA48 8x10mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline
D FD FE SD D1
E
E1
SE ddd
BALL "A1"
A
e
b A1
A2
BGA-Z28
Note: Drawing is not to scale.
Table 11. TFBGA48 8x10mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data
Symbol A A1 A2 b D D1 ddd E E1 e FD FE SD SE 10.000 5.250 0.750 2.125 2.375 0.375 0.375 9.900 - - - - - - 8.000 3.750 0.350 7.900 - 0.260 0.900 0.450 8.100 - 0.100 10.100 - - - - - - 0.3937 0.2067 0.0295 0.0837 0.0935 0.0148 0.0148 0.3898 - - - - - - 0.3150 0.1476 0.0138 0.3110 - millimeters Typ Min Max 1.200 0.0102 0.0354 0.0177 0.3189 - 0.0039 0.3976 - - - - - - Typ inches Min Max 0.0472
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M68AR512D
PART NUMBERING Table 12. Ordering Information Scheme
Example: Device Type M68 Mode A = Asynchronous Operating Voltage R = 1.65 to 1.95V Array Organization 512 = 8 Mbit (512K x16) Option 1 D = 2 Chip Enable; Write and Standby from UB and LB Option 2 L = L-Die N = N-Die Speed Class 70 = 70 ns Package ZB = TFBGA48, 6x7mm, 6x8 ball array 0.75 mm pitch (1) ZB = TFBGA48, 8x10mm, 6x8 ball array 0.75 mm pitch (2) Operative Temperature 1 = 0 to 70 C 6 = -40 to 85 C Shipping T = Tape & Reel Packing
Note: 1. TFBGA48, 6x7mm is available only for the M68AR512DN part. 2. TFBGA48, 8x10mm is available only for the M68AR512DL part.
M68AR512
D
N
70 ZB
6
T
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M68AR512D
REVISION HISTORY Table 13. Document Revision History
Date August 2001 08-Oct-2001 Version -01 -02 First Issue Document status moved to Preliminary Data Document status moved to Data Sheet Temperature range 1 (0 to 70C) added Tables 3, 5, 6, 7, 8 and 9 clarified Figures 7, 8, 9, 10, 11 and 12 clarified Document globally revised Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 04 equals 4.0). Part number changed. Part number changed and new salestype added TFBGA48 8x10mm package added (Figure 16, Table 11) Revision Details
18-Mar-2002
-03
17-May-2002
-04
02-Oct-2002
4.1
09-Oct-2002
4.2
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M68AR512D
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
19/19

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